Deaprom having amorphous silicon carbide gate insulator

ABSTRACT

A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. Ser. No. 09/134,713,filed on Aug. 14, 1998; which is a divisional of U.S. Ser. No.08/902,843, filed Jul. 29, 1997, now abandoned; each of which isincorporated herein by reference in its entirety.

This application is related to the following co-pending, commonlyassigned U.S. patent applications: “MEMORY DEVICE,” Ser. No. 08/902,133;“DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIUM ALUMIUM NITRIDEGATE,” Ser. No. 08/902,098, now issued as U.S. Pat. No. 6,031,263;“CARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS,” Ser. No.08/903,453; “TRANSISTOR WITH VARIABLE ELECTRON AFFINITY GATE AND METHODSOF FABRICATION AND USE,” Ser. No. 08/903,452, now abandoned; “SILICONCARBIDE GATE TRANSISTOR AND FABRICATION PROCESS,” Ser. No. 08/903,486,now issued as U.S. Pat. No. 6,936,849; and “TRANSISTOR WITH SILICONOXYCARBIDE GATE AND METHODS OF FABRICATION AND USE,” Ser. No.08/902,132, now issued as U.S. Pat. No. 5,886,368; each of which wasfiled on Jul. 29, 1997, and each of which disclosure is hereinincorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuittechnology, including dynamic random access memories (DRAMs) andelectrically erasable and programmable read only memories (EEPROMS), andparticularly, but not by way of limitation, to a floating gatetransistor memory that is dynamically electrically alterable andprogrammable.

BACKGROUND OF THE INVENTION

Dynamic random access memories (DRAMs) are data storage devices thatstore data as charge on a storage capacitor. A DRAM typically includesan array of memory cells. Each memory cell includes a storage capacitorand an access transistor for transferring charge to and from the storagecapacitor. Each memory cell is addressed by a word line and accessed bya bit line. The word line controls the access transistor such that theaccess transistor controllably couples and decouples the storagecapacitor to and from the bit line for writing and reading data to andfrom the memory cell.

The storage capacitor must have a capacitance that is large enough toretain a charge sufficient to withstand the effects of parasiticcapacitances, noise due to circuit operation, and access transistorreverse-bias junction leakage currents between periodic data refreshes.Such effects can result in erroneous data. Obtaining a large capacitancetypically requires a storage capacitor having a large area. However, amajor goal in DRAM design is to minimize the area of a DRAM memory cellto allow cells to be more densely packed on an integrated circuit die sothat more data can be stored on smaller integrated circuits.

In achieving the goal of increasing DRAM array capacity by increasingcell density, the sufficient capacitance levels of the DRAM storagecapacitors must be maintained. A “stacked storage cell” design canincrease the cell density to some degree. In this technique, two or morecapacitor conductive plate layers, such as polycrystalline silicon(polysilicon or poly), are deposited over a memory cell accesstransistor on a semiconductor wafer. A high dielectric constant materialis sandwiched between these capacitor plate layers. Such a capacitorstructure is known as a stacked capacitor cell (STC) because the storagecapacitor plates are stacked on top of the access transistor. However,formation of stacked capacitors typically requires complicated processsteps. Stacked capacitors also typically increase topographical featuresof the integrated circuit die, making subsequent lithography andprocessing, such as for interconnection formation, more difficult.Alternatively, storage capacitors can be formed in deep trenches in thesemiconductor substrate, but such trench storage capacitors also requireadditional process complexity. There is a need in the art to furtherincrease memory storage density without adding process complexity oradditional topography.

Electrically erasable and programmable read only memories (EEPROMs)provide nonvolatile data storage. EEPROM memory cells typically usefield-effect transistors (FETs) having an electrically isolated(floating) gate that affects conduction between source and drain regionsof the FET. A gate dielectric is interposed between the floating gateand an underlying channel region between source and drain regions. Acontrol gate is provided adjacent to the floating gate, separatedtherefrom by an intergate dielectric.

In such memory cells, data is represented by charge stored on thepolysilicon floating gates, such as by hot electron injection orFowler-Nordheim tunneling during a write operation. Fowler-Nordheimtunneling is typically used to remove charge from the polysiliconfloating gate during an erase operation. However, the relatively largeelectron affinity of the polysilicon floating gate presents a relativelylarge tunneling barrier energy at its interface with the underlying gatedielectric. The large tunneling barrier energy provides longer dataretention times than realistically needed. For example, a data chargeretention time at 85 □ C is estimated to be in millions of years forsome floating gate memory devices. The large tunneling barrier energyalso increases the voltages and time needed to store and remove chargeto and from the polysilicon floating gate. “Flash” EEPROMs, which havean architecture that allows the simultaneous erasure of many floatinggate transistor memory cells, require even longer erasure times toaccomplish this simultaneous erasure. The large erasure voltages neededcan result in hole injection into the gate dielectric. This can causeerratic overerasure, damage to the gate dielectric, and introduction oftrapping states in the gate dielectric. The high electric fields thatresult from the large erasure voltages can also result in reliabilityproblems, leading to device failure. There is a need in the art toobtain floating gate transistors that allow the use of lower programmingand erasure voltages and shorter programming and erasure times.

SUMMARY OF THE INVENTION

The present invention includes a memory cell that allows the use oflower programming and erasure voltages and shorter programming anderasure times by providing a storage electrode for storing charge andproviding an adjacent amorphous silicon carbide (a-SiC) insulator.

In one embodiment, the memory cell includes a floating gate transistor,having a reduced barrier energy between the floating gate and anamorphous silicon carbide (a-SiC) insulator. A refresh circuit allowsdynamic refreshing of charge stored on the floating gate. The barrierenergy can be lowered to a desired value by selecting the appropriatematerial composition of the a-SiC insulator. As a result, lowerprogramming and erasure voltages and shorter programming and erasuretimes are obtained.

Another aspect of the present invention provides a method of using afloating gate transistor having a reduced barrier energy between afloating gate electrode and an adjacent a-SiC insulator. Data is storedby changing the charge of the floating gate. Data is refreshed based ona data charge retention time established by the barrier energy. Data isread by detecting a conductance between a source and a drain. The largetransconductance gain of the memory cell of the present inventionprovides a more easily detected signal and reduces the required datastorage capacitance value and memory cell size when compared to aconventional dynamic random access memory (DRAM) cell.

The present invention also includes a method of forming a floating gatetransistor. Source and drain regions are formed. An a-SiC gate insulatoris formed. A floating gate is formed, such that the floating gate isisolated from conductors and semiconductors. The a-SiC gate insulatorprovides a relatively short data charge retention time, butadvantageously provides a shorter write/programming and erase times,making operation of the present memory speed competitive with a DRAM.

The present invention also includes a memory device that is capable ofproviding short programming and erase times, low programming and erasevoltages, and lower electric fields in the memory cell for improvedreliability. The memory device includes a refresh circuit and aplurality of memory cells. Each memory cell includes a transistor. Eachtransistor includes a source region, a drain region, a channel regionbetween the source and drain regions, and a floating gate that isseparated from the channel region by an a-SiC gate insulator. Thetransistor also includes a control gate located adjacent to the floatinggate and separated therefrom by an intergate dielectric. The memorydevice includes flash electrically erasable and programmable read onlymemory (EEPROM), dynamic random access memory (DRAM), and dynamicallyelectrically alterable and programmable read only memory (DEAPROM)embodiments.

The memory cell of the present invention provides a reduced barrierenergy, large transconductance gain, an easily detected signal, andreduces the required data storage capacitance value and memory cellsize. The lower barrier energy increases tunneling current and alsoadvantageously reduces the voltage required for writing and erasing thefloating gate transistor memory cells. For example, conventionalpolysilicon floating gate transistors typically require complicated andnoisy on-chip charge pump circuits to generate the large erasurevoltage, which typically far exceeds other voltages required on theintegrated circuit. The present invention allows the use of lowererasure voltages that are more easily provided by simpler on-chipcircuits. Reducing the erasure voltage also lowers the electric fields,minimizing reliability problems that can lead to device failure, andbetter accommodating downward scaling of device dimensions.Alternatively, the thickness of the gate insulator can be increased fromthe typical thickness of a silicon dioxide gate insulator to improvereliability or simplify processing, since the lower barrier energyallows easier transport of charge across the gate insulator byFowler-Nordheim tunneling.

According to another aspect of the invention, the shorter retention timeof data charges on the floating electrode, resulting from the smallerbarrier energy, is accommodated by refreshing the data charges on thefloating electrode. By decreasing the data charge retention time andperiodically refreshing the data, the write and erase operations can beseveral orders of magnitude faster such that the present memory is speedcompetitive with a DRAM. In this respect, the memory operates similar toa memory cell in DRAM, but avoids the process complexity, additionalspace needed, and other limitations of forming stacked or trench DRAMcapacitors.

The memory cell of the present invention can be made smaller than aconventional DRAM memory cell. Moreover, because the storage capacitorof the present invention is integrally formed as part of the transistor,rather than requiring complex and costly non-CMOS stacked and trenchcapacitor process steps, the memory of the present invention should becheaper to fabricate than DRAM memory cells, and should more easilyscale downward as CMOS technology advances.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like numerals describe substantially similar componentsthroughout the several views.

FIG. 1 is a simplified schematic/block diagram illustrating generallyone embodiment of a memory including reduced barrier energy floatingelectrode memory cells.

FIG. 2 is a cross-sectional view that illustrates generally a floatinggate transistor embodiment of a memory cell provided by the presentinvention.

FIG. 3 is an energy band diagram that illustrates generally conductionband energy levels in a floating gate transistor provided by the presentinvention.

FIG. 4 is a graph comparing barrier energy vs. tunneling distance for aconventional floating gate transistor and one embodiment of a thepresent invention having a lower barrier energy.

FIG. 5 is a graph that illustrates generally the relationship betweenFowler-Nordheim tunneling current density vs. the barrier energy Φ_(GI)at various parameterized values E₁<E₂<E₃ of an electric field.

FIG. 6 illustrates generally how the barrier energy affects the timeneeded to perform write and erase operations by Fowler-Nordheimtunneling for a particular voltage.

FIG. 7 is a graph that illustrates generally charge density vs.write/erase time for three different embodiments of a floating gate FET.

FIG. 8 is a cross-sectional view, similar to FIG. 2, but having a largerarea control gate-floating gate capacitor than the floatinggate-substrate capacitor.

FIG. 9A is a schematic diagram, labeled prior art, that illustratesgenerally a conventional DRAM memory cell.

FIG. 9B is a schematic diagram that illustrates generally one embodimentof a floating gate FET memory cell according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include anysemiconductor-based structure having an exposed surface with which toform the integrated circuit structure of the invention. Wafer andsubstrate are used interchangeably to refer to semiconductor structuresduring processing, and may include other layers that have beenfabricated thereupon. Both wafer and substrate include doped and undopedsemiconductors, epitaxial semiconductor layers supported by a basesemiconductor or insulator, as well as other semiconductor structureswell known to one skilled in the art. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

The present invention discloses a dynamic electrically alterableprogrammable read only memory (DEAPROM) cell. The memory cell has afloating electrode, which is defined as an electrode that is“electrically isolated” from conductors and semiconductors by aninsulator such that charge storage upon and removal from the floatingelectrode depends upon charge conduction through the insulator. In oneembodiment, described below, the floating electrode is a floating gateelectrode in a floating gate field-effect transistor, such as used inflash electrically erasable and programmable read only memories(EEPROMs). However, a capacitor or any other structure having a floatingelectrode and adjacent insulator could also be used according to thetechniques of the present invention described below. According to oneaspect of the present invention, a barrier energy between the floatingelectrode and the insulator is lower than the barrier energy betweenpolycrystalline silicon (polysilicon) and silicon dioxide (SiO₂), whichis approximately 3.3 eV. According to another aspect of the presentinvention, the shorter retention time of data charges on the floatingelectrode, resulting from the smaller barrier energy, is accommodated byrefreshing the data charges on the floating electrode. In this respect,the memory operates similar to a memory cell in a dynamic random accessmemory (DRAM). These and other aspects of the present invention aredescribed in more detail below.

FIG. 1 is a simplified schematic/block diagram illustrating generallyone embodiment of a memory 100 according to one aspect of the presentinvention, in which reduced barrier energy floating electrode memorycells are incorporated. Memory 100 is referred to as a dynamicelectrically alterable programmable read only memory (DEAPROM) in thisapplication, but it is understood that memory 100 possesses certaincharacteristics that are similar to DRAMs and flash EEPROMs, asexplained below. For a general description of how a flash EEPROMoperates, see B. Dipert et al., “Flash Memory Goes Mainstream,” IEEESpectrum, pp. 48-52 (October 1993), which is incorporated herein byreference. Memory 100 includes a memory array 105 of multiple memorycells 110. Row decoder 115 and column decoder 120 decode addressesprovided on address lines 125 to access the addressed memory cells inmemory array 105. Command and control circuitry 130 controls theoperation of memory 100 in response to control signals received oncontrol lines 135 from a processor 140 or other memory controller duringread, write, refresh, and erase operations. Command and controlcircuitry 130 includes a refresh circuit for periodically refreshing thedata stored on floating gate transistor or other floating electrodememory cells 110. Voltage control 150 provides appropriate voltages tothe memory cells during read, write, refresh, and erase operations.Memory 100, as illustrated in FIG. 1, has been simplified for thepurpose of illustrating the present invention and is not intended to bea complete description. Only the substantial differences between DEAPROMmemory 100 and conventional DRAM and flash EEPROM memories are discussedbelow.

FIG. 2 is a cross-sectional view that illustrates generally, by way ofexample, but not by way of limitation, one floating gate transistorembodiment of a memory cell 110. Other structural arrangements offloating gate transistors are included within the present invention.Also included are any memory cells that incorporate a floating electrode(such as a floating electrode capacitor) having, at an interface betweenthe floating electrode an adjacent insulator, a barrier energy that isless than the barrier energy at a polysilicon-SiO₂ interface. In theembodiment of FIG. 2, memory cell 110 includes a floating gate FET 200,which is illustrated as an n-channel FET, but understood to include ap-channel FET embodiment as well.

FET 200 includes a source 205, a drain 210, a floating gate 215electrode, and a control gate 220 electrode. A gate insulator 225 isinterposed between floating gate 215 and substrate 230. An intergateinsulator 235 is interposed between floating gate 215 and control gate220. In one embodiment, substrate 230 is a bulk semiconductor, such assilicon. In another embodiment, substrate 230 includes a thinsemiconductor surface layer formed on an underlying insulating portion,such as in a semiconductor-on-insulator (SOI) or other thin filmtransistor technology. Source 205 and drain 210 are formed byconventional complementary metal-oxide-semiconductor (CMOS) processingtechniques. Source 205 and drain 210 are separated by a predeterminedlength for forming an inversion channel 240 therebetween.

FIG. 3 is an energy band diagram that illustrates generally theconduction band energy levels in floating gate 215, gate insulator 225,and substrate 230. Electron affinities χ₂₁₅, χ₂₂₅, and χ₂₃₀ describefloating gate 215, gate insulator 225, and substrate 230, respectively,when measured with respect to a vacuum level 300. A barrier energyΦ_(GI), which describes the barrier energy at the interface betweenfloating gate 215 and gate insulator 225, is given by a difference inelectron affinities, as illustrated in Equation 1.Φ_(GI)=χ₂₁₅−χ₂₂₅  (1)A barrier energy Φ_(SG), which describes the barrier energy at theinterface between substrate 230 and gate insulator 225, is given by adifference in electron affinities, as illustrated in Equation 2.Φ_(SG)=χ₂₃₀−χ₂₂₅  (2)Silicon (monocrystalline or polycrystalline Si) has an electron affinityχ₂₁₅≈4.2 eV. Silicon dioxide (SiO₂) has an electron affinity, χ₂₂₅, ofabout 0.9 eV. The resulting barrier energy at a conventional Si—SiO₂interface between a floating gate and a gate insulator is approximatelyequal to 3.3 eV. One aspect of the present invention provides a barrierenergy Φ_(GI) that is less than the 3.3 eV barrier energy of aconventional Si—SiO₂ interface.

According to one aspect of the invention, the interface between floatinggate 215 and gate insulator 225 provides a smaller barrier energy Φ_(GI)than the 3.3 eV barrier energy at an interface between polysilicon andsilicon dioxide, such as by an appropriate selection of the materialcomposition of one or both of floating gate 215 and gate insulator 225.In one embodiment, the smaller barrier energy Φ_(GI) is obtained byforming floating gate 215 from a material having a smaller electronaffinity χ₂₁₅ than polysilicon. In one embodiment, for example,polycrystalline or microcrystalline silicon carbide (SiC) is used as thematerial for forming floating gate 215. In another embodiment, thesmaller barrier energy Φ_(GI) is obtained by forming gate insulator 225from a material having a higher electron affinity χ₂₂₅ than SiO₂. In oneembodiment, for example, amorphous SiC is used as the material forforming gate insulator 225. In yet another embodiment, the smallerbarrier energy Φ_(GI) is obtained by a combination of forming floatinggate 215 from a material having a smaller electron affinity χ₂₁₅ thanpolysilicon and also forming gate insulator 225 from a material having ahigher electron affinity χ₂₂₅ than SiO₂.

The smaller barrier energy Φ_(GI) provides current conduction acrossgate insulator 225 that is easier than for a polysilicon-SiO₂ interface.The present invention includes any mechanism of providing such easiercurrent conduction across gate insulator 225, including, but not limitedto “hot” electron injection, thermionic emission, Schottky emission,Frenkel-Poole emission, and Fowler-Nordheim tunneling. Such techniquesfor transporting charge carriers across an insulator, such as gateinsulator 225, are all enhanced by providing a smaller barrier energyΦ_(GI) according to the techniques of the present invention. Thesetechniques allow increased current conduction, current conduction atlower voltages across gate insulator 225 and lower electric fields ingate insulator 225, shorter data write and erase times, use of a thickerand more reliable gate insulator 225, and other advantages explainedbelow.

FIG. 4 is a graph illustrating generally barrier energy versus tunnelingdistance for a conventional polysilicon-SiO₂ interface having a 3.3 eVbarrier energy. FIG. 4 also illustrates barrier energy versus tunnelingdistance for an interface according to the present invention that has abarrier energy of Φ_(GI)≈1.08 eV, which is selected as an illustrativeexample, and not by way of limitation. The smaller barrier energy Φ_(GI)reduces the energy to which the electrons must be excited to be storedon or removed from the floating gate 215, such as by thermal emissionover the barrier. The smaller barrier energy Φ_(GI) also reduces thedistance that electrons have to traverse, such as by Fowler-Nordheimtunneling, to be stored upon or removed from floating gate 215. In FIG.4, “do” represents the tunneling distance of a conventional floatinggate transistor due to the 3.3 eV barrier energy represented by thedashed line “OLD”. The tunneling distance “dn” corresponds to a floatinggate transistor according to the present invention and its smallerbarrier energy, such as Φ_(GI)≈1.08 eV, for example, represented by thedashed line “NEW”. Even a small reduction in the tunneling distanceresults in a large increase in the tunneling probability, as describedbelow, because the tunneling probability is an exponential function ofthe reciprocal of the tunneling distance.

The Fowler-Nordheim tunneling current density in gate insulator 225,which is illustrated approximately by Equation 3 below, is described ina textbook by S. M. Sze, “Physics of Semiconductor Devices,” John Wiley& Sons, New York (1969), p. 496. $\begin{matrix}{J = {{AE}^{2}{\mathbb{e}}^{({- \frac{B}{B}})}}} & (3)\end{matrix}$In Equation 3, J is the current density in units of amperes/cm², E isthe electric field in gate insulator 225 in units of volts/cm and A andB are constants, which are particular to the material of gate insulator225, that depend on the effective electron mass in the gate insulator225 material and on the barrier energy Φ_(GI). The constants A and Bscale with the barrier energy Φ_(GI), as illustrated approximately byEquations 4 and 5, which are disclosed in S. R. Pollack et al.,“Electron Transport Through Insulating Thin Films,” Applied Solid StateScience, Vol. 1, Academic Press, New York, (1969), p. 354.$\begin{matrix}{A\quad{\alpha\left( \frac{1}{\Phi_{GI}} \right)}} & (4) \\{B\quad{\alpha\left( \Phi_{GI} \right)}^{\frac{3}{2}}} & (5)\end{matrix}$For a conventional floating gate FET having a 3.3 eV barrier energy atthe interface between the polysilicon floating gate and the SiO₂ gateinsulator, A=5.5×10⁻¹⁶ amperes/Volt² and B=7.07×10⁷ Volts/cm, asdisclosed in D. A. Baglee, “Characteristics and Reliability of 100 ÅOxides,” Proc. 22nd Reliability Symposium, (1984), p. 152. One aspect ofthe present invention includes selecting a smaller barrier energy Φ_(GI)such as, by way of example, but not by way of limitation, Φ_(GI)≈≈1.08eV. The constants A and B for Φ_(GI)≈1.08 eV can be extrapolated fromthe constants A and B for the 3.3 eV polysilicon-SiO₂ barrier energyusing Equations 4 and 5. The barrier energy Φ_(GI)≈1.08 eV yields theresulting constants A=1.76×10⁻¹⁵ amperes/Volt² and B=1.24×10⁷ Volts/cm.

FIG. 5 is a graph that illustrates generally the relationship betweenFowler-Nordheim tunneling current density vs. the barrier energy Φ_(GI),such as at various parameterized values E₁<E₂<E₃ of an electric field ingate insulator 225. The tunneling current density increases as electricfield is increased. The tunneling current also increases by orders ofmagnitude as the barrier energy Φ_(GI) is decreased, such as byselecting the materials for floating gate 215 and gate insulator 225 orotherwise reducing the barrier energy Φ_(GI) according to the techniquesof the present invention. In particular, FIG. 5 illustrates a comparisonbetween tunneling current densities at the 3.3 eV barrier energy of aconventional polysilicon-SiO₂ interface and at the illustrative examplebarrier energy Φ_(GI)≈1.08 eV for which constants A and B wereextrapolated above. Reducing the 3.3 eV barrier energy to Φ_(GI)≈1.08 eVincreases the tunneling current density by several orders of magnitude.

FIG. 6 is a conceptual diagram, using rough order of magnitudeestimates, that illustrates generally how the barrier energy affects thetime needed to perform write and erase operations by Fowler-Nordheimtunneling for a particular voltage, such as across gate insulator 225.FIG. 6 also illustrates how the barrier energy affects data chargeretention time, such as on floating gate 215 at a temperature of 250degrees Celsius. Both write and erase time 600 and data charge retentiontime 605 are decreased by orders of magnitude as the barrier energy isdecreased, according to the present invention, from the conventionalpolysilicon-SiO₂ interface barrier energy of 3.3 eV to the illustrativeexample lower barrier energy Φ_(GI)≈1.08 eV for which constants A and Bwere extrapolated above.

The lower barrier energy Φ_(GI) and increased tunneling currentadvantageously provides faster write and erase times. This isparticularly advantageous for “flash” EEPROMs or DEAPROMs in which manyfloating gate transistor memory cells must be erased simultaneously,requiring a longer time to transport the larger quantity of charge. Fora flash EEPROM using a polysilicon floating gate transistor having anunderlying SiO₂ gate insulator 225, the simultaneous erasure of a blockof memory cells requires a time that is on the order of milliseconds.The write and erase time of the floating gate FET 200 is illustratedapproximately by Equation 6. $\begin{matrix}{t = {{\int_{0}^{t}\quad{\mathbb{d}t}} = {\int_{o}^{Q}{\left( \frac{1}{J_{225} - J_{235}} \right)\quad{\mathbb{d}Q}}}}} & (6)\end{matrix}$In Equation 6, t is the write/erase time, J₂₂₅ and J₂₃₅ are therespective tunneling current densities in gate dielectric 225 andintergate dielectric 235, Q is the charge density in Coulombs/cm² onfloating gate 215. Equation 6 is evaluated for a specific voltage oncontrol gate 220 using Equations 7 and 8. $\begin{matrix}{E_{225} = \frac{V_{220}}{\left\lbrack {d_{225} + {d_{235}\left( \frac{ɛ_{225}}{ɛ_{235}} \right)}} \right\rbrack - \frac{Q}{\left\lbrack {ɛ_{225} + {ɛ_{235}\left( \frac{d_{225}}{d_{235}} \right)}} \right\rbrack}}} & (7) \\{E_{235} = \frac{V_{220}}{\left\lbrack {d_{235} + {d_{225}\left( \frac{ɛ_{235}}{ɛ_{225}} \right)}} \right\rbrack - \frac{Q}{\left\lbrack {ɛ_{235} + {ɛ_{225}\left( \frac{d_{235}}{d_{225}} \right)}} \right\rbrack}}} & (8)\end{matrix}$In Equations 7 and 8, V₂₂₀ is the voltage on control gate 220, E₂₂₅ andE₂₃₅ are the respective electric fields in gate insulator 225 andintergate insulator 235, d₂₂₅ and d₂₃₅ are the respective thicknesses ofgate insulator 225 and intergate insulator 235, and ε₂₂₅ and ε₂₃₅ arethe respective permittivities of gate insulator 225 and intergateinsulator 235.

FIG. 7 is a graph that illustrates generally charge density vs.write/erase time for three different embodiments of the floating gateFET 200, each of which have a polysilicon floating gate 215, by way ofillustrative example. Line 700 illustrates generally, by way of example,but not by way of limitation, the charge density vs. write/erase timeobtained for a floating gate FET 200 having a 100 Å SiO₂ gate insulator225 and a 150 Å SiO₂ (or thinner oxynitride equivalent capacitance)intergate insulator 235.

Line 705 is similar to line 700 in all respects except that line 705illustrates a floating gate FET 200 in which gate insulator 225comprises a material having a higher electron affinity χ₂₂₅ than SiO₂,thereby providing a lower barrier energy Φ_(GI) at the interface betweenpolysilicon floating gate 215 and gate insulator 225. The increasedtunneling current results in shorter write/erase times than thoseillustrated by line 700.

Line 710 is similar to line 705 in all respects except that line 710illustrates a floating gate FET 200 in which gate insulator 225 has alower barrier energy Φ_(GI) than for line 705, or intergate insulator235 has a higher permittivity ε₂₃₅ than for line 705, or control gate220 has a larger area than floating gate 215, such as illustrated by wayof example by the floating gate FET 800 in the cross-sectional view ofFIG. 8. As seen in FIG. 8, the area of a capacitor formed by the controlgate 220, the floating gate 215, and the intergate insulator 235 islarger than the area of a capacitor formed by the floating gate 215, thegate insulator 225, and the inversion channel 240 underlying gateinsulator 225. Alternatively, or in combination with the techniquesillustrated in FIG. 8, the intergate insulator 235 can have a higherpermittivity than the permittivity of silicon dioxide.

As illustrated in FIG. 7, the barrier energy Φ_(GI) can be selected toreduce the write/erase time. In one embodiment, by way of example, butnot by way of limitation, the barrier energy Φ_(GI) is selected toobtain a write/erase time of less than or equal to 1 second, asillustrated in FIG. 7. In another embodiment, by way of example, but notby way of limitation, the barrier energy Φ_(GI) is selected to obtain awrite/erase time of less than or equal to 1 millisecond, as illustratedin FIG. 7. Other values of write/erase time can also be obtained byselecting the appropriate value of the barrier energy Φ_(GI).

The lower barrier energy Φ_(GI) and increased tunneling current alsoadvantageously reduces the voltage required for writing and erasing thefloating gate transistor memory cells 110. For example, conventionalpolysilicon floating gate transistors typically require complicated andnoisy on-chip charge pump circuits to generate the large erasurevoltage, which typically far exceeds other voltages required on theintegrated circuit. The present invention allows the use of lowererasure voltages that are more easily provided by simpler on-chipcircuits. Reducing the erasure voltage also lowers the electric fields,minimizing reliability problems that can lead to device failure, andbetter accommodating downward scaling of device dimensions. In oneembodiment, the barrier energy Φ_(GI) is selected, as described above,to obtain an erase voltage of less than the 12 Volts required by typicalEEPROM memory cells.

Alternatively, the thickness of the gate insulator 225 can be increasedfrom the typical thickness of a silicon dioxide gate insulator toimprove reliability or simplify processing, since the lower barrierenergy Φ_(GI) allows easier transport of charge across the gateinsulator 225 by Fowler-Nordheim tunneling.

The lower barrier energy Φ_(GI) also decreases the data charge retentiontime of the charge stored on the floating gate 215, such as fromincreased thermal excitation of stored charge over the lower barrierΦ_(GI). However, conventional polysilicon floating gates and adjacentSiO₂ insulators (e.g., 90 Å thick) have a data charge retention timeestimated in the millions of years at a temperature of 85 degrees C.,and estimated in the 1000 hour range even at extremely high temperaturessuch as 250 degrees C. Since such long data charge retention times arelonger than what is realistically needed, a shorter data chargeretention time can be accommodated in order to obtain the benefits ofthe smaller barrier energy Φ_(GI). In one embodiment of the presentinvention, by way of example, but not by way of limitation, the barrierenergy Φ_(GI) is lowered to Φ_(GI)≈1.08 eV by appropriately selectingthe composition of the materials of floating gate 215 and gate insulator225, as described below. As a result, an estimated data charge retentiontime of approximately 40 seconds at a high temperature, such as 250degrees C., is obtained.

According to one aspect of the present invention, the data stored on theDEAPROM floating gate memory cell 110 is periodically refreshed at aninterval that is shorter than the data charge retention time. In oneembodiment, for example, the data is refreshed every few seconds, suchas for an embodiment having a high temperature retention time ofapproximately 40 seconds for Φ_(GI)≈1.08 eV. The exact refresh rate canbe experimentally determined and tailored to a particular process offabricating the DEAPROM. By decreasing the data charge retention timeand periodically refreshing the data, the write and erase operations canbe several orders of magnitude faster, as described above with respectto FIG. 7.

FIGS. 9A and 9B are schematic diagrams that respectively illustrategenerally a conventional DRAM memory cell and the present invention'sfloating gate FET 200 embodiment of memory cell 110. In FIG. 9A, theDRAM memory cell includes an access FET 900 and stacked or trenchstorage capacitor 905. Data is stored as charge on storage capacitor 905by providing a control voltage on control line 910 to activate FET 900for conducting charge. Data line 915 provides a write voltage to conductcharge across FET 900 for storage on storage capacitor 905. Data is readby providing a control voltage on control line 910 to activate FET 900for conducting charge from storage capacitor 905, thereby incrementallychanging a preinitialized voltage on data line 915. The resulting smallchange in voltage on data line 915 must be amplified by a senseamplifier for detection. Thus, the DRAM memory cell of FIG. 9Ainherently provides only a small data signal. The small data signal isdifficult to detect.

In FIG. 9B, the DEAPROM memory cell 110 according to the presentinvention includes floating gate FET 200, having source 205 coupled to aground voltage or other reference potential. Data is stored as charge onfloating gate 215 by providing a control voltage on control line 920 anda write voltage on data line 925 for hot electron injection orFowler-Nordheim tunneling. This is similar to conventional EEPROMtechniques, but advantageously uses the reduced voltages and/or ashorter write time of the present invention.

The DEAPROM memory cell 110 can be smaller than the DRAM memory cell ofFIG. 9A, allowing higher density data storage. The leakage of chargefrom floating gate 215 can be made less than the reverse-bias junctionleakage from storage capacitor 905 of the DRAM memory cell by tailoringthe barrier energy Φ_(GI) according to the techniques of the presentinvention. Also, the DEAPROM memory cell advantageously uses the largetransconductance gain of the floating gate FET 200. The conventionalDRAM memory cell of FIG. 9A provides no such gain; it is read bydirectly transferring the data charge from storage capacitor 905. Bycontrast, the DEAPROM memory cell 110 is read by placing a read voltageon control line 920, and detecting the current conducted through FET200, such as at data line 925. The current conducted through FET 200changes significantly in the presence or absence of charge stored onfloating gate 215. Thus, the present invention advantageously providesan large data signal that is easy to detect, unlike the small datasignal provided by the conventional DRAM memory cell of FIG. 9A.

For example, the current for floating gate FET 200 operating in thesaturation region can be approximated by Equation 9. $\begin{matrix}{I_{DS} = {\frac{1}{2}\mu\quad{C_{0}\left( \frac{W}{L} \right)}\left( {V_{G} - V_{T}} \right)^{2}}} & (9)\end{matrix}$In Equation 9, I_(DS) is the current between drain 210 and source 205,C_(o) is the capacitance per unit area of the gate insulator 225, W/L isthe width/length aspect ratio of FET 200, V_(G) is the gate voltageapplied to control gate 220, and V_(T) is the turn-on threshold voltageof FET 200.

For an illustrative example, but not by way of limitation, aminimum-sized FET having W/L=1, can yield a transconductance gain ofapproximately 71 μA/Volt for a typical process. In this illustrativeexample, sufficient charge is stored on floating gate 215 to change theeffective threshold voltage V_(T) by approximately 1.4 Volts, therebychanging the current I_(DS) by approximately 100 microamperes. Thissignificant change in current can easily be detected, such as bysampling or integrating over a time period of approximately 10nanoseconds, for example, to obtain a detected data charge signal of1000 fC. Thus, the DEAPROM memory cell 110 is capable of yielding adetected data charge signal that is approximately an order of magnitudelarger than the typical 30 fC to 100 fC data charges typically stored onDRAM stacked or trench capacitors. Since DEAPROM memory cell 110requires a smaller capacitance value than a conventional DRAM memorycell, DEAPROM memory cell 110 can be made smaller than a conventionalDRAM memory cell. Moreover, because the CMOS-compatible DEAPROM storagecapacitor is integrally formed as part of the transistor, rather thanrequiring complex and costly non-CMOS stacked and trench capacitorprocess steps, the DEAPROM memory of the present invention should becheaper to fabricate than DRAM memory cells, and should more easilyscale downward as CMOS technology advances.

Amorphous SiC Gate Insulator Embodiment

In one embodiment, the present invention provides a DEAPROM having astorage element including a gate insulator 225 that includes anamorphous silicon carbide (a-SiC). For example, one embodiment of amemory storage element having an a-SiC gate insulator 225 is describedin Forbes et al. U.S. patent application Ser. No. 08/903,453 entitledCARBURIZED SILICON GATE INSULATORS FOR INTEGRATED CIRCUITS, filed on thesame day as the present patent application, and which disclosure isherein incorporated by reference. The a-SiC inclusive gate insulator 225provides a higher electron affinity χ₂₂₅ than the approximately 0.9 eVelectron affinity of SiO₂. For example, but not by way of limitation,the a-SiC inclusive gate insulator 225 can provide an electron affinityχ₂₂₅≈3.24 eV.

An a-SiC inclusive gate insulator 225 can also be formed using othertechniques. For example, in one embodiment gate insulator 225 includes ahydrogenated a-SiC material synthesized by ion-implantation of C₂H₂ intoa silicon substrate 230. For example, see G. Comapagnini et al.“Spectroscopic Characterization of Annealed Si_(1-x)C_(x) FilmsSynthesized by Ion Implantation,” J. of Materials Research, Vol. 11, No.9, pp. 2269-73, (1996). In another embodiment, gate insulator 225includes an a-SiC film that is deposited by laser ablation at roomtemperature using a pulsed laser in an ultrahigh vacuum or nitrogenenvironment. For example, see A. L. Yee et al. “The Effect of Nitrogenon Pulsed Laser Deposition of Amorphous Silicon Carbide Films:Properties and Structure,” J. Of Materials Research, Vol. 11, No. 8, pp.1979-86 (1996). In another embodiment, gate insulator 225 includes ana-SiC film that is formed by low-energy ion-beam assisted deposition tominimize structural defects and provide better electricalcharacteristics in the semiconductor substrate 230. For example, see C.D. Tucker et al. “Ion-beam Assisted Deposition of Nonhydrogenated a-Si:Cfilms,” Canadian J. Of Physics, Vol. 74, No. 3-4, pp. 97-101 (1996). Theion beam can be generated by electron cyclotron resonance from an ultrahigh purity argon (Ar) plasma.

In another embodiment, gate insulator 225 includes an a-SiC film that issynthesized at low temperature by ion beam sputtering in a reactive gasenvironment with concurrent ion irradiation. For example, see H. Zhanget al., “Ion-beam Assisted Deposition of Si-Carbide Films,” Thin SolidFilms, Vol. 260, No. 1, pp. 32-37 (1995). According to one technique,more than one ion beam, such as an Ar ion beam, are used. A first Ar ionbeam is directed at a Si target material to provide a Si flux forforming SiC gate insulator 225. A second Ar ion beam is directed at agraphite target to provide a C flux for forming SiC gate insulator 225.The resulting a-SiC gate insulator 225 is formed by sputtering onsubstrate 230. In another embodiment, gate insulator 225 includes an SiCfilm that is deposited on substrate 230 by DC magnetron sputtering atroom temperature using a conductive, dense ceramic target. For example,see S. P. Baker et al. “D-C Magnetron Sputtered Silicon Carbide,” ThinFilms, Stresses and Mechanical Properties V. Symposium, pp. Xix+901,227-32 (1995). In another embodiment, gate insulator 225 includes a thina-Si_(1-x)C_(x):H film that is formed by HF plasma ion sputtering of afused SiC target in an Ar—H atmosphere. For example, see N. N. Svirkovaet al. “Deposition Conditions and Density-of-States Spectrum ofa-Si_(1-x)C_(x):H Films Obtained by Sputtering,” Semiconductors, Vol.28, No. 12, pp. 1164-9 (1994). In another embodiment, radio frequency(RF) sputtering is used to produce a-SiC films. For example, see Y.Suzaki et al. “Quantum Size Effects of a-Si(:H)/a-SiC(:H) MultilayerFilms Prepared by RF Sputtering,” J. Of Japan Soc. Of PrecisionEngineering, Vol. 60, No. 3, pp. 110-18 (1996). Bandgaps of a-Si, a-SiC,a-Si:H, and a-SiC:H have been found to be 1.22 eV, 1.52 eV, 1.87 eV, and2.2 eV respectively.

In another embodiment, gate insulator 225 is formed by chemical vapordeposition (CVD) and includes an a-SiC material. According to onetechnique, gate insulator 225 includes a-Si_(1-x)C_(x):H deposited byplasma enhanced chemical vapor deposition (PECVD). For example, see I.Pereyra et al. “Wide Gap a-Si_(1-x)C_(x):H Thin Films Obtained UnderStarving Plasma Deposition Conditions,” J. Of Non-crystalline Solids,Vol. 201, No. 1-2, pp. 110-118 (1995). According to another technique,mixed gases of silane and methane can be used to form a-Si_(1-x)C_(x):Hgate insulator 225. For example, the source gas can include silane inmethane with additional dilution in hydrogen. In another embodiment,gate insulator 225 includes a clean a-Si_(1-x)C_(x) material formed byhot-filament assisted CVD. For example, see A. S. Kumbhar et al. “Growthof Clean Amorphous Silicon Carbon Alloy Films By Hot-Filament AssistedChemical Vapor Deposition Technique,” Appl. Phys. Letters, Vol. 66, No.14, pp. 1741-3 (1995). In another embodiment, gate insulator 225includes a-SiC formed on a crystalline Si substrate 230 by inductivelycoupled plasma CVD, such as at 450 degrees Celsius, which can yielda-SiC rather than epitaxially grown polycrystalline or microcrystallineSiC. The resulting a-SiC inclusive gate insulator 225 can provide anelectron affinity χ₂₂₅≈3.24 eV, which is significantly larger than the0.9 eV electron affinity obtainable from a conventional SiO₂ gateinsulator. For example, see J. H. Thomas et al. “Plasma Etching andSurface Analysis of a-SiC:H Films Deposited by Low Temperature PlasmaEnhanced Vapor Deposition,” Gas-phase and Surface Chemistry inElectronic Materials Processing Symposium, Materials Research Soc., pp.Xv+556, 445-50 (1994).

Gate insulator 225 can be etched by RF plasma etching using CF₄O₂ inSF₆O₂. Self-aligned source 205 and drain 210 can then be formed usingconventional techniques for forming a FET 200 having a floating(electrically isolated) gate 215, or in an alternate embodiment, anelectrically interconnected (driven) gate.

CONCLUSION

The present invention provides a DEAPROM cell. The memory cell has afloating electrode, such as a floating gate electrode in a floating gatefield-effect transistor. According to one aspect of the invention, abarrier energy between the floating electrode and the insulator is lowerthan the barrier energy between polysilicon and SiO₂, which isapproximately 3.3 eV, by using an amorphous silicon carbide (a-SiC) gateinsulator adjacent to the floating gate. The memory cell also provideslarge transconductance gain, which provides a more easily detectedsignal and reduces the required data storage capacitance value.

According to another aspect of the invention, the shorter retention timeof data charges on the floating electrode, resulting from the smallerbarrier energy, is accommodated by refreshing the data charges on thefloating electrode. By decreasing the data charge retention time andperiodically refreshing the data, the write and erase operations can beseveral orders of magnitude faster. In this respect, the memory operatessimilar to a memory cell in DRAM, but avoids the process complexity,additional space needed, and other limitations of forming stacked ortrench DRAM capacitors.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that theabove-described embodiments can be used in combination, and anyarrangement which is calculated to achieve the same purpose may besubstituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A method of forming a memory cell comprising: forming a source regionin a substrate; forming a drain region in the substrate, a channelregion being between the source region and the drain region in thesubstrate; forming a floating gate; and forming an amorphous siliconcarbide (a-SiC) insulator between the floating gate and the channelregion in the substrate, the amorphous silicon carbide (a-SiC) insulatorbeing in contact with both the floating gate and the substrate.
 2. Themethod of claim 1 wherein forming a floating gate and forming anamorphous silicon carbide (a-SiC) insulator further comprises forming atleast one of the floating gate and the a-SiC insulator to have anelectron affinity such that a barrier energy, defined as a differencebetween an electron affinity of the floating gate and an electronaffinity of the a-SiC insulator, is less than approximately 3.3 eV. 3.The method of claim 2 wherein forming at least one of the floating gateand the a-SiC insulator further comprises forming the floating gate andthe a-SiC insulator such that the barrier energy facilitates a datacharge retention time on the floating gate of less than or equal toapproximately 40 seconds at 250 degrees Celsius.
 4. The method of claim2 wherein forming at least one of the floating gate and the a-SiCinsulator further comprises forming the floating gate and the a-SiCinsulator such that the barrier energy facilitates a floating gate erasetime of less than or equal to approximately 1 second.
 5. The method ofclaim 2 wherein forming at least one of the floating gate and the a-SiCinsulator further comprises forming the floating gate and the a-SiCinsulator such that the barrier energy facilitates a floating gate erasevoltage of less than approximately 12 Volts.
 6. The method of claim 1wherein forming an amorphous silicon carbide (a-SiC) insulator furthercomprises forming the a-SiC insulator to have an electron affinity thatis less than an electron affinity of silicon dioxide (SiO2).
 7. Themethod of claim 1 wherein forming a floating gate further comprisesforming the floating gate to have a smaller electron affinity thanpolycrystalline silicon.
 8. The method of claim 1 wherein forming afloating gate and forming an amorphous silicon carbide (a-SiC) insulatorfurther comprises forming at least one of the floating gate and thea-SiC insulator to have an electron affinity such that a barrier energy,defined as a difference between an electron affinity of the floatinggate and an electron affinity of the a-SiC insulator, is less thanapproximately 2.0 eV.
 9. The method of claim 1 wherein forming afloating gate further comprises forming the floating gate such that thefloating gate is isolated from conductors and semiconductors.
 10. Themethod of claim 1 wherein: forming a floating gate further comprisesforming the floating gate such that the floating gate istransconductively capacitively coupled to the channel region; andforming a source region further comprises forming the source region in asilicon substrate.
 11. A method for forming a transistor comprising:forming a source region in a silicon substrate; forming a drain regionin the substrate; forming a channel region in the substrate between thesource region and the drain region; and forming a floating gateseparated from the channel region by an amorphous silicon carbide(a-SiC) insulator, the amorphous silicon carbide (a-SiC) insulator beingin contact with both the substrate and the floating gate.
 12. The methodof claim 11 wherein forming a floating gate further comprises forming atleast one of the floating gate and the a-SiC insulator to have anelectron affinity such that a barrier energy, defined as a differencebetween an electron affinity of the floating gate and an electronaffinity of the a-SiC insulator, is less than approximately 3.3 eV. 13.The method of claim 11 wherein forming a floating gate further comprisesforming at least one of the floating gate and the a-SiC insulator tohave an electron affinity such that the barrier energy provides a datacharge retention time of the transistor that is adapted for dynamicrefreshing of charge stored on the floating gate.
 14. The method ofclaim 11, further comprising forming a control electrode opposite fromthe floating gate and separated from the floating gate by an intergateinsulator.
 15. The method of claim 14 wherein forming a controlelectrode further comprises forming the control electrode with a shapesuch that an area of a capacitor formed by the control electrode, thefloating gate, and the intergate insulator is larger than an area of acapacitor formed by the floating gate, the a-SiC insulator, and thechannel region.
 16. The method of claim 14 wherein forming a controlelectrode further comprises forming the intergate insulator to have apermittivity that is higher than a permittivity of silicon dioxide. 17.A method of forming a floating gate transistor, comprising: formingsource and drain regions in a silicon substrate; forming an amorphoussilicon carbide (a-SiC) gate insulator on the substrate over a channelregion located between the source and drain regions in the substrate;and forming a floating gate on the a-SiC gate insulator, wherein formingan amorphous silicon carbide (a-SiC) gate insulator and forming afloating gate further comprises forming the a-SiC gate insulator andforming the floating gate such that a barrier energy, defined as adifference between an electron affinity of the floating gate and anelectron affinity of the a-SiC gate insulator, is less thanapproximately 3.3 eV.
 18. The method of claim 17 wherein forming anamorphous silicon carbide (a-SiC) gate insulator further comprisesforming an amorphous silicon carbide (a-SiC) gate insulator byion-implantation of C2H2 into a silicon substrate.
 19. The method ofclaim 17, wherein forming an amorphous silicon carbide (a-SiC) gateinsulator includes forming an amorphous silicon carbide (a-SiC) gateinsulator by laser ablation at room temperature using a pulsed laser inan ultrahigh vacuum or nitrogen environment.
 20. The method of claim 17,wherein forming an amorphous silicon carbide (a-SiC) gate insulatorincludes forming an amorphous silicon carbide (a-SiC) gate insulator bylow-energy ion-beam assisted deposition in order to minimize structuraldefects and provide better electrical characteristics in the substrate.21. The method of claim 17, wherein forming an amorphous silicon carbide(a-SiC) gate insulator includes forming an amorphous silicon carbide(a-SiC) gate insulator by ion beam sputtering in a reactive gasenvironment with concurrent ion irradiation.
 22. The method of claim 17,wherein forming an amorphous silicon carbide (a-SiC) gate insulatorincludes forming an amorphous silicon carbide (a-SiC) gate insulator byDC magnetron sputtering at room temperature using a conductive, denseceramic target.
 23. The method of claim 17, wherein forming an amorphoussilicon carbide (a-SiC) gate insulator includes forming an amorphoussilicon carbide (a-SiC) gate insulator by HF plasma ion sputtering of afused SiC target in an Ar—H atmosphere.
 24. The method of claim 17,wherein forming an amorphous silicon carbide (a-SiC) gate insulatorincludes forming an amorphous silicon carbide (a-SiC) gate insulator byradio frequency (RF) sputtering.
 25. The method of claim 17, whereinforming an amorphous silicon carbide (a-SiC) gate insulator includesforming an amorphous silicon carbide (a-SiC) gate insulator by chemicalvapor deposition (CVD).
 26. The method of claim 17, wherein forming anamorphous silicon carbide (a-SiC) gate insulator includes forming anamorphous silicon carbide (a-SiC) gate insulator by inductively coupledplasma CVD, such as at 450 degrees Celsius, which can yield a-SiC ratherthan epitaxially grown polycrystalline or microcrystalline SiC.
 27. Amethod of forming a floating gate transistor comprising: forming ann-type source region and an n-type drain region in a silicon substrate;forming an amorphous silicon carbide (a-SiC) gate insulator on thesubstrate over a channel region in the substrate, the channel regionbeing located between the source region and the drain region; andforming a polysilicon floating gate on the a-SiC gate insulator.
 28. Themethod of claim 27 wherein: forming an n-type source region comprisesforming an n+-type source region and an n+-type drain region in asilicon substrate; forming an amorphous silicon carbide (a-SiC) gateinsulator further comprises forming the a-SiC gate insulator byion-implantation of C2H2 into the substrate to have an electron affinitythat is less than an electron affinity of silicon dioxide (SiO2);forming a polysilicon floating gate further comprises forming the a-SiCgate insulator and forming the polysilicon floating gate such that abarrier energy, defined as a difference between an electron affinity ofthe polysilicon floating gate and an electron affinity of the a-SiC gateinsulator, is less than approximately 3.3 eV; and further comprising:forming an intergate insulator on the polysilicon floating gate; andforming a control electrode on the intergate insulator.